The design and manufacture of very large scale integrated (VLSI) digital circuits involves the steps of digital circuit design, choice of device technology, process technology, device technology performance performance verification, and incorporation of the technology into VLSI products. The verification step consists of applying a sequence of known digital signals, representative of the signals which the device must process in practice, and monitoring the resulting output of the new circuit technology being tested. Optimally, these signals should be sequences at least as random, i.e., non-recurrent, as would be consistent with signals applied in practice, and of length sufficient to permit a number of different sequences so as to drive the circuit into a large enough number of states so that a good level of confidence in the circuit performance can be obtained.
Other features which are desirable in generating such circuit test signals are reproducibility and high frequency of the signal sequences, simplicity of the signal generating circuitry, and low-power requirements of the signal-generating circuitry.
To try to meet all these disparate requirements and accomplish the verification with a test circuitry prototype having as small a number of stages as is consistent with a reasonable assurance of reliable circuit verification, present methods employ the use of the device technology in ring oscillators, divide-by-n counters and non-feedback shift registers. While marginally adequate for low- and medium-scale integrated circuit testing, these generating circuits produce signal sequences which are very regular, i.e. recurrent, and not representative of sequences present in VLSI circuits. Furthermore, their non-recurrent sequence length is limited by the number of stages employed within the chosen test circuitry. The circuit parameters obtained by such testing tend to be optimistic compared to that realized by the device when employed on a chip under actual operating circuit conditions.